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Sheet目录3882

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PIC18FXX39

DS30485A-page 176

Preliminary

2002 Microchip Technology Inc.

17.3

USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition, enable bit SPEN (RCSTA<7>) is set in order

to configure the RC6/TX/CK and RC7/RX/DT I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

17.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 17-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXREG is empty and inter-

rupt bit TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE, and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit TRMT (TXSTA<1>)

shows the status of the TSR register. TRMT is a read

only bit, which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory, so it is not

available to the user.

To set up a Synchronous Master Transmission:

Initialize the SPBRG register for the appropriate

baud rate (Section 17.1).

Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

TABLE 17-8:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Note:

TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction

cycle

following

the

load

instruction.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

—

TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

—

TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

—

TMR2IP TMR1IP 0000 0000 0000 0000

RCSTA

SPEN

RX9

SREN

CREN ADDEN

FERR

OERR

RX9D

0000 -00x

TXREG USART Transmit Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

SPBRG Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Master Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

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